Abstract
In this work, we introduce a generalized concept for low-latency masking that is applicable to any implementation and protection order, and (in its most extreme form) does not require on-the-fly randomness. The main idea of our approach is to avoid collisions of shared variables in nonlinear circuit parts and to skip the share compression. We show the feasibility of our approach on a full implementation of a one-round unrolled Ascon variant and on an AES S-box case study. Additionally, we discuss possible trade-offs to make our approach interesting for practical implementations. As a result, we obtain a first-order masked AES S-box that is calculated in a single clock cycle with rather high implementation costs (60.7 kGE), and a two-cycle variant with much less implementation costs (6.7 kGE). The side-channel resistance of our Ascon S-box designs up to order three are then verified using the formal analysis tool of [BGI+18]. Furthermore, we introduce a taint checking based verification approach that works specifically for our low-latency approach and allows us to verify large circuits like our low-latency AES S-box design in reasonable time.
Highlights
Boolean masking is one of the most popular and well-studied countermeasures against side-channel analysis attacks, like differential power analysis [KJJ99] or electromagnetic emanation analysis [QS01]
Our low-latency approach is presented in Section 3 in which we show that masking not necessarily introduces latency or requires online randomness
We note the existence of domain-oriented masking (DOM)-dep. masked AND gates which are resilient to variable collisions for the price of more randomness and chip area
Summary
Boolean masking is one of the most popular and well-studied countermeasures against side-channel analysis attacks, like differential power analysis [KJJ99] or electromagnetic emanation analysis [QS01]. The protection against these kinds of attacks, does not come for free. Masking works by disguising side-channel information of sensitive variables and intermediates by randomizing their representation. For a Boolean masking with d + 1 fresh random shares, where d is the so-called protection order, we can represent a masked variable x as the sum over its shares xi so that at all times x =. All operations are performed on the shares xi in such a way that at no time any intermediate result is statistically dependent on more than one share of x to guarantee security in the so-called probing model of Ishai et al [ISW03]
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More From: IACR Transactions on Cryptographic Hardware and Embedded Systems
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