Abstract
A linear RC delay modeling algorithm is presented to model empirically the timing delays in CMO circuits. The empirical model, an multidimensional function of various circuit and device parameters, is shown to be simplified to a two-dimensional model which estimates the delay of a CMOS gate in terms of the generic RC delay and the rise/fall time of the input transition. Accuracy limitations of the linear RC delay model are discussed, and the empirically generated delay models, based on the generic RC model, are shown to improve the accuracy problem. The model has been installed in an experimental simulator and tested for various circuits. Comparisons are made with SPICE to validate the model's reliability. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
