Abstract

This dissertation presents a framework for the formal verification of standard embedded components such us bus protocol, microprocessor, memory blocks, various IP blocks, and a software component. It includes a model checking of embedded systems components. The algorithms are modeled on SystemC and transformed on Promela language (PROcess or PROtocol MEta LAnguage) with the integration of LTL (Linear Temporal Logic) properties extracting from state machines in order to reduce verification complexity. Thus, SysVerPml is not only dedicated to verifying generated properties but also for the automation integration of other properties in models if needed. In the following, we will provide the answer to the problems of component representation on the design system, what properties are appropriate for each component, and how to verify properties.

Highlights

  • Verification can be applied to discover errors early in the SOC (System On Chip) design against properties expressed as part of the requirements

  • The formal verification technology is divided into three methods: equivalence checking, model checking, and theorem proving [2], [3]

  • Model checking is an algorithmic technique for determining whether a system satisfies a formal specification expressed as a temporal logic formula, where properties are the direct representation of a design’s behavior [5]

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Summary

INTRODUCTION

Verification can be applied to discover errors early in the SOC (System On Chip) design against properties expressed as part of the requirements. The main idea in our approach is that the number of states of a design is exponential to the number of variables and the width of each variable To attain this first aim as explained in our previous article [9] the modeling methodology of a system must exhibit the execution semantics instead of encompassing it inside an execution-scheduler. In order to allow new and old systems integration, any process interaction which might be useful for inter-system integration must not be cut in the final system model. The challenge of this approach is to guarantee that the abstract model is exact to the granularity of programs behaviors states. We conclude the resume with tests of the performance verification of our framework followed by conclusion

VERIFICATION ENVIRONMENT
CASE STUDY
CONCLUSION
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