Generating deterministic unordered test patterns with counters

Abstract

We study the behavior of counter-based schemes as very low hardware overhead built-in mechanisms for reproducing unordered test patterns. We show that a small number of seeds, each defining a test pattern generation session, can result in an economical design in terms of both time and hardware. We present counter-based schemes with a trade-off on the time and hardware overhead. Experimental results on the ISCAS'85 benchmarks and comparisons with other built-in mechanisms show that the proposed schemes constitute a promising technique for effective built-in deterministic test pattern generation.