Abstract
A general-purpose clocked gate driver (CGD) IC to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with 0.18µm BCD process has 63 PMOS and 63 NMOS driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 25-MHz clock (= 40-ns time step control). In the 500-V switching measurements, the proposed CGD reduces the IC overshoot by 25% and 41% and the energy loss by 38% and 55% for Si-IGBT and SiC-MOSFET, respectively.
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