Generalized parallelization methodology for heterogeneous HPC platforms

Abstract

Latest High Performance Computing (HPC) platforms are built with heterogeneous chips such as multicore microprocessors and multicore GPUs (Graphic Processing units), thus they are commonly called as Heterogeneous High Performance Computing (HPC) platforms. Parallelizing applications on such platforms is mostly dominated by SIMD style of parallelism mainly to exploit GPUs' excellent floatingpoint performance. However, it is a restricted parallel model because the multiple CPU cores are not participating in the parallel execution, thus the full performance potential of heterogeneous architectures is not exploited. In this paper, we propose a generalized parallelization methodology to efficiently map applications onto the heterogeneous architectures and to exploit their full performance potential. For the methodology, we develop strategies to map parallel tasks onto different components of the heterogeneous architectures. A general parallel execution model beyond SIMD is adopted in the task mapping.