Generalized interleaving network based on configurable QPP architecture for parallel turbo decoder

Abstract

Quadratic permutation polynomial (QPP) interleaver is a contention-free interleaver which is suitable for parallel turbo decoder implementation. In this paper, a systematic recursive method to design configurable QPP interleaving multistage network is proposed based on the property of QPP. Due to the nature of recursion, the proposed network for 2n-level parallel turbo decoder can be used for any 2i parallelism (0 < i ≤ n) without the need to redesign additional network for different level of parallelism. Address generator is modified to provide control signals to the network. Furthermore, the proposed QPP architecture is generalized to support arbitrary contention-free interleavers by appending an additional specially designed network. When the whole network is used in multi-standard design, the appended network can be turned off at QPP interleaver mode to reduce more than 49% dynamic power for parallelism greater than 16.