Generalization of Logic Picture-based power estimation tool

Abstract

In this paper, the Logic Picture-based power estimation tool is extended to include more features. The Logic Picture is a technique used for CMOS dynamic power estimation in both combinational and sequential logic circuits. This technique proved to be more accurate and less time consuming compared to other techniques. This work enhances the tool by calculating the maximum power consumption in sequential circuits. Furthermore, it is extended to include all types of Flip-Flops and takes into account the power consumption in the internal nodes of these Flip-Flops. Finally, it is shown how to incorporate all the features and enhancements for Design Space Exploration in sequential circuits.