Abstract
Recently the growth of III–V semiconductors on Si substrates has received considerable attention. In particular heteroepitaxy of systems with larger lattice mismatch than GaAs on Si has been reported (1). The possibility of integrating both high speed and optoelectronic, III–V devices with Si technology is extremely attractive. Furthermore large diameter Si wafers provide low cost robust and virtually defect free substrates. However, many materials problems arise due to the large lattice parameter and thermal expansion coefficient differences and difficulties in the nucleation of polar semiconductors on non-polar surfaces (2).
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