Gating Aware Error Injection

Abstract

Error injection is one of the most commonly used techniques for estimating the reliability of a given hardware design. While error injection in dynamic simulation is widely used in the industry, other methods exist as well, e.g. hardware error injection and fault-tolerance analysis using formal verification. As covering the entire space of all possible fault injections is impractical, nearly all workload-based error injection methods (e.g. simulation or emulation techniques) use a statistical approach for error injection, i.e. they only inject a fraction of all possible faults. As a result, the statistical fault injection approach is much more efficient in characterizing the overall reliability of the design than in finding particular reliability-related bugs. On the other hand, the formal-based approach guarantees full coverage of the design space, including under all possible faults, granted the formal analysis can be completed. However, performing formal verification on design hierarchies with error detection and recovery logic is usually unfeasible. To address the challenge of effectively finding reliability-related bugs on large industrial designs, this paper proposes a novel approach which is aimed at finding a particular kind of design bugs related to gating conditions which correspond to error detection logic. We present an automated method for identifying those gating conditions and generating a gating-aware fault injection module. Experimental results on a real microprocessor arithmetical unit demonstrates the effectiveness of our method in finding real design bugs using relatively small amount of error injection tests.