Gateless and Capacitorless Germanium Biristor with a Vertical Pillar Structure

Hagyoul Bae,Geon-Beom Lee,Da-Jin Kim,Jun-Young Park,Myung-Su Kim,Yang-Kyu Choi,Jae Hur

doi:10.3390/mi12080899

Abstract

For the first time, a novel germanium (Ge) bi-stable resistor (biristor) with a vertical pillar structure was implemented on a bulk substrate. The basic structure of the Ge pillar-typed biristor is a p-n-p bipolar junction transistor (BJT) with an open base (floating), which is equivalent to a gateless p-channel metal oxide semiconductor field-effect transistor (MOSFET). In the pillar formation, we adopted an amorphous carbon layer to protect the Ge surface from both physical and chemical damage by subsequent processes. A hysteric current-voltage (I-V) characteristic, which results in a sustainable binary state, i.e., high current and low current at the same voltage, can be utilized for a memory device. A lower operating voltage with high current was achieved, compared to a Si biristor, due to the low energy bandgap of pure Ge.

Highlights

As memory devices continue to be scaled down for high density integration, the conventional 1-transistor and 1-capacitor dynamic random-access memory (1T/1C DRAM)cell used for large storage capacity is facing process challenges
One is a planar structure that was implemented on a silicon-on-insulator (SOI) wafer [7,8] for a floating body and the other is a vertical structure that was fabricated on a bulk-Si wafer [9,10]
A vertical Ge biristor with a gateless p-n-p structure, which can be applied in the gateless and capacitorless DRAM, was demonstrated for the first time

Summary

Introduction

As memory devices continue to be scaled down for high density integration, the conventional 1-transistor and 1-capacitor dynamic random-access memory (1T/1C DRAM). In order to solve these technological limitations, the floating body-based dynamic random-access memory (DRAM) cell with a capacitorless structure has been under active research and development to improve fabrication simplicity and cell area scalability [4,5,6]. Such DRAM has at least three terminals: gate, source, and drain. In order to make the heavily doped junctions, a p+ emitter and collector were used because of high boron solubility in Ge. By employing pure Ge, a lower operating voltage and higher onstate current were achieved, compared with a Si-based biristor. The pillar-shaped vertical structure can be an optimized structure to minimize the area of the biristor

Device Fabrication

Discussion

LUthe compared with the reported from the Si

Conclusions