Abstract
AbstractLateral nMOSFETs have been fabricated on 4H-SiC utilizing deposited dielectrics and gate-last processing. A bi-layer dielectric was utilized consisting of thin nitrided SiO2 covered by 25nm of Al2O3 deposited using atomic layer deposition. Field-effect mobility and threshold voltage (VT) were found to vary with SiC nitric oxide (NO) anneal temperature. High peak mobility values of 106 cm2/V·s were obtained, with a corresponding VT of 0.8 V, using an 1175 °C 20 min NO anneal of the SiC before Al2O3 deposition. Constant voltage stressing (CVS) of the gate (3 MV/cm) for 1000s induces a VT increase of only 0.12 V for the devices stressed at RT, whereas a VT shift of 0.34 V occurs for devices stressed at 150 °C. Heating unstressed devices to 200 °C reveals a stable VT with temperature. Negative charge in the gate region allows for the attainment of positive VT, while VT stability does not suffer.
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