Abstract
In this study, a gate-stack engineering technique is proposed as a means of improving the performance of a 28 nm low-power (LP) high-k/metal-gate (HK/MG) device. In detail, it was experimentally verified that HfSiO thin films can replace HfSiON congeners, where the latter are known to have a good thermal budget and/or electrical characteristics, to boost the device performance under a limited thermal budget. TiN engineering for the gate-stack in the 28 nm LP HK/MG device was used to suppress the gate leakage current. Using the proposed fabrication method, the on/off current ratio (Ion/Ioff) was improved for a given target Ion, and the gate leakage current was appropriately suppressed. Comparing the process-of-record device against the 28 nm LP HK/MG device, the thickness of the electrical oxide layer in the new device was reduced by 3.1% in the case of n-type field effect transistors and by 10% for p-type field effect transistors. In addition, the reliability (e.g., bias temperature instability, hot carrier injury, and time-dependent dielectric breakdown) of the new device was evaluated, and it was observed that there was no conspicuous risk. Therefore, the HfSiO film can afford reliable performance enhancement when employed in the 28 nm LP HK/MG device with a limited thermal budget.
Highlights
In the case of the process-of-record (POR) metal oxide semiconductor (MOS) structure, SiO2 /HfSiON/TiN was used as an interlayer (IL), high-k material, and metal-gate, respectively, and they were deposited in order
Compared to the POR device, the electrical oxide thickness in the new device was reduced by 3.1% for the n-type field-effect transistor (NFET) and
The reliability of the samples fabricated by the newly proposed process flow was evaluated in terms of hotcarrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB)
Summary
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. To meet the needs of a hyper-connected society, the need for various types of integrated circuit (IC) chips has dramatically increased. Fin-shaped field-effect transistors (FinFETs) have been widely adopted in low-power/high-performance IC chips over the last a few decades, they are still not very cost-effective for some applications. If a technique for dramatically improving the performance of planar bulk transistors in legacy technology (e.g., 28 nm technology) can be developed, it would potentially replace cutting-edge
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