Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design

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Previously the gate matrix technique was used to lay out the RALU section of a CMOS 32-bit CPU chip. It took 1.2 Engineer-Years to complete the layout of the RALU that contained more than 20,000 transistors with multiple-bus structure. The average packing density was 840 μm/sup 2/ per transistor in 2.5 μm design rules. Recently we have applied the gate matrix technique to lay out the highly complex control of the CPU. With a well-structured layout strategy, the gate matrix layout provided (1) adaptability to evolving logic design with short turnaround times, (2) compatibility with computer aids in layout verification, (3) high packing density competitive with hand layout, and (4) compatibility with a team approach to layout. It took 6.5 Engineer-Years to complete the error-free layout of over 7,000 transistors although the logic design was continuously evolving during the layout period. More than half of the layout efforts were due to logic changes. The average packing density in the final layout of the random control logic was about 1,500 μm/sup 2/ per transistor with 2.5 μm design rules.