Abstract
A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm2/Vs are achieved for the gate length and width of 0.2 µm and 30µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10−8 A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.
Highlights
The continuous scaling of MOS devices leads to some fundamental limits such as short channel effects (SCEs) and high leakage current related to having lower gate controllability on the channel
The results reveal significant increasing in drain current (Id) by scaling the Lg down to 200 nm (Fig 4a)
Gm measurement (Fig 4b) shows the same trend but the peaks of the gm shift to negative gate voltage by reduction of the Lg. This behaviour can imply the negative shift in threshold voltage (Vth) due to the scaling of the gate length, which is in agreement with the results shown in Id-Vg graph (Fig 4a)
Summary
The continuous scaling of MOS devices leads to some fundamental limits such as short channel effects (SCEs) and high leakage current related to having lower gate controllability on the channel This can make a crucial challenge against the performance improvements of the scaled devices mentioned by the International Technology Roadmap of Semiconductors (ITRS). Several new technologies such as highk dielectrics [1], metal gate electrodes [2], stressors [3], and new transistor architectures based on silicon-on-insulator (SOI), such as Fin FETs [4], Junctionless transistors [5] or gate-all-around FETs [6], have been proposed Another important option, in order to overcome the scaling limitation, is to seek any possible alternative of ‘‘beyond Si’’ channel materials, such as Germanium and III–V compound semiconductors. Some high performance devices have been reported for self-aligned InGaAs MOSFETs with high-k gate dielectrics formed by ALD [11,12,13]
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