Gate length scalability of n-MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures

Abstract

Gate length scalability of LDD and non-LDD n-MOSFETs are investigated in terms of resistance to short-channel effects. Extremely small gate electrodes are delineated using electron beam direct writing and highly selective dry-etching techniques. An LDD MOSFET with As-implanted 15-nm-deep junctions shows a superior scalability down to 30 nm. In contrast, in the case of a non-LDD MOSFET having Sb-/spl delta/-doped 18-nm-deep junctions, the drain induced barrier lowering (DIBL) mechanism limits the minimum gate length to around 80 nm, at which favorable device operation is achieved. The difference between built in potential of source/drain junctions (around 0.1 eV) of LDD and non-LDD devices is found to remarkably affect short channel characteristics in the sub-0.1-/spl mu/m region.