Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors

Abstract

The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated. It is found that the gate current of the mesa-type HFETs is higher than that of the planar devices, particularly at low biases. Analyses of the gate current considering different transport mechanisms yielded identical thermionic currents (i.e., an identical Schottky barrier height) but a significantly higher leakage component in the mesa-type HFETs than in the planar devices. This additional current component observed in the mesa-type devices shows a nearly ohmic behavior. Mapping by the electron-beam induced current technique confirms an enhanced current located under the expanded gate contact and on the part of the mesa-sidewall, where the gate contact is placed. Two-dimensional simulation of the device structure shows that considerable part of the gate leakage current flows through the GaN buffer layer. These results underline the importance of a proper design of the device structure and layout (i.e., the use of planar structure with device insulation prepared by ion implantation rather than by mesa technique), and of the preparation of the GaN buffer (it should be semi-insulating) in order to fabricate reliable, low leakage current GaN-based HFETs.