Gate-Induced Drain Leakage Currents in Metal Oxide Semiconductor Field Effect Transistors with High-κ Dielectric

Abstract

In this study, gate-induced drain leakage (GIDL) characteristics were studied for different device structures having high-κ dielectric as a gate dielectric and/or a spacer. A guideline for reducing the GIDL current is given in terms of the gate dielectric and the spacer structures. The structures were compared in terms of dielectric constant, equivalent oxide thickness (EOT), and drain-induced barrier lowering (DIBL). The E-field contour, which is responsible for the GIDL, was shown. It was also shown that the device structure having a gate dielectric stack of high-κ gate dielectric/buffer SiO2 spacer is feasible for the suppression of the GIDL. As the EOT becomes smaller by using high-κ, the GIDL becomes severe.