Gate delay analysis in two-step recess gate InGaAs-HEMTs with slant field plates

Abstract

We fabricated InGaAs-HEMTs with two-step recess (TSR) gates and SiCN-based multi-step slant field plates (FPs). The results indicate that the FP enhances the breakdown voltage (BV) of the TSR gate devices, and the TSR gate improves the current gain cutoff frequency (f T ) in comparison with the conventional recess gate devices with FPs. The results also indicate that the TSR gate makes BV lower than the conventional gate devices with the same FP structure, and FP decreases f T of the devices with TSR gates. The gate delay time analysis indicates that FPs increase the parasitic gate delay time. Additionally, the FPs with a few steps increases the intrinsic gate delay as well as the parasitic gate delay while the 10-step slant FPs does not affect the intrinsic gate delay. Therefore, the slant FPs is a promising approach to mitigate the trade-off between BV and f T in InGaAs-HEMTs.