Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate

Abstract

For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conventional bulk-Si FinFET. It provides a stable way for the introduction of nanowire transistors in the FinFETs process for mass productions. The fabricated n-type transistors with the effective nanowire diameter (DNW) of 12 nm∼17 nm and the gate length of 100 nm demonstrated excellent subthreshold characteristics (subthreshold swing = 64 mV/V and drain induced barrier lowering = 24 mV/V). Meanwhile, it’s found that the H2 baking process as well as the optimized interface gate oxidation on NW channels greatly improved the device’s SS and off-current parameters.