Abstract

All-solid-state lithium ion batteries may overcome safety issues in future energy storage systems, when a non-flammable solid electrolyte instead of a liquid electrolyte is applied. Garnet-type Li7La3Zr2O12 (LLZO) is an encouraging choice due to its high Li+ conductivity and its chemical stability against lithium metal [1]. However, low-resistance LLZO/Li interfaces are deteriorated by incomplete adhesion of lithium metal onto LLZO and by surface contamination [2]. The resulting inhomogeneous distribution of contact areas may be more prone to dendrite formation. Previous studies [3,4] indicate that LLZO/Li interface quality is significantly improved by metallic buffer layers.In this study, we aim for a reliable preparation of low-resistance interfaces between solid electrolyte and lithium metal. At first, magnetron sputtering is applied to deposit an indium buffer layer of 50 to 500 nm thickness onto the polished and cleaned electrolyte surface. For cell assembly, lithium foil is put on both sides of an In-coated LLZO pellet and the test cell is heated to 220°C in argon atmosphere. After that, microstructure and electrochemical properties of the symmetric cells are analyzed. We improved cross-section sample preparation to inspect the quality of LLZO/In/Li interfaces over hundreds of µm. Scanning electron microscopy (SEM, cf. figure 1) confirms excellent adhesion between lithium and LLZO. We use a dry inert atmosphere during preparation, handling and transfer of our samples to avoid artifacts and sample degradation. The FEI Helios G4 FX microscope enables correlative SEM imaging by simultaneous acquisition of up to four different detector signals for interface topography and material contrast. Local chemical composition at the interface is analyzed by energy dispersive X-ray spectroscopy and electron-beam damage is minimized for SEM imaging by selecting optimum electron energies.Electrochemical impedance spectroscopy (EIS) followed by data evaluation via the distribution of relaxation times (DRT) and equivalent circuit modelling [5] deliver the proportional contributions of grain, grain boundaries and interfaces to the total impedance of symmetric cells (Li/In/LLZO/In/Li). Interface microstructures and EIS measurements are correlated for samples with different buffer layer characteristics to allow targeted optimization. We compare the pristine state of the test cells to samples that have been cycled with different current densities.

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