Abstract
The concept for and design/fabrication of a GaN power transistor with integrated thermal management is presented. Key elements of the design, including those supporting enhancement-mode operation, high breakdown voltages and low on-resistance are described in detail. The importance of surface preparation and growth of high-k gate dielectrics using atomic layer deposition is summarized. Aspects of barrier design and surface passivation to promote low access resistance including lattice matched barriers and novel low-temperature AlN passivations are discussed. Finally, the integration of nanocrystalline diamond coatings on both the top-side and the back-side of the device for thermal management are described. Initial performance assessments of each of these components, as measured in the device operation, are presented and future efforts are highlighted.
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