Abstract

Power gating is often used to reduce dynamic power consumption in microelectronics systems. There exist several methodologies for the implementation of power gating with varying effect on performance. In this work, we propose a new power gating utilization methodology that is based on controlling the instruction scheduler from a game theoretical perspective. The latter targets a best power gating rate with minimal possible loss of performance. The methodology combines Bayesian, Mixed Strategy, and Repeated games. We implemented the methodology and tested it on a randomly generated set of instructions. Results show an enhancement in total power consumed by functional units with no major effect on performance. These results are promising and motivate to follow on investigation.

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