Abstract
This paper proposes a methodology for substrate noise reduction in mixed-signal integrated circuits (IC) by using a globally-asynchronous locally-synchronous (GALS) approach for digital system integration. For this purpose the harmonic balanced partitioning strategy is proposed. It is shown that by converting a synchronous design into a plesiochronous GALS design with M locally-synchronous modules (LSMs), a theoretical limit of spectral peak attenuation corresponds to 20logM. This model is evaluated by numerical simulations in MATLAB. Based on the proposed partitioning scheme, a methodology for GALS partitioning for optimal substrate noise reduction is developed. Finally the corresponding low-noise GALS design flow is proposed, based on a custom noise optimization tool named EMIAS. The flow is evaluated on a realistic design example.
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