Gain Enhancement techniques of 0.13 μm CMOS Low Noise Amplifier

Abstract

This paper presents a 130nm CMOS low noise amplifier design by using inductively generated cascode topology with gain enhancement technique. A narrow band low noise amplifier is designed with an operating frequency of 2.4GHz for WLAN application. In the proposed LNA, the single stage of cascode LNA procedure is utilized to improve the noise figure and isolation. The LNA gives a high increase and low noise figure and great reverse isolation over the recurrence range just as good stability. The low noise amplifier is biased at 1.2V supply voltage and completely organized with the input impedance of 50 Ω. An inductor is added at the drain of the main transistor to reduce the noise contribution of cascode transistor. This LNA manages to achieve the noise figure, NF of 0.94 dB, gain, S 21 of 23.36 dB, S 11 is -11.36 dB with the power consumption of 12.09mW. The reverse voltage gain, S 12 obtain is -40.61 dB and the output return loss, S22 is -3.85 dB. The third input intercept, the IIP3 value from simulated is -14.33 dBm.