Abstract
Two gain enhancement techniques for monolithically integrated monopole antennas are presented in this work. The proposed configurations have been designed in a standard 0.13 μm SiGe BiCMOS process. In the first one, Split Ring Resonators (SRRs) have been combined with Localized Backside Etching (LBE). These etched parts are removed locally from the silicon substrate, reducing the losses and thus contributing to increase the gain of the monopole antenna. In the second technique, an on-chip monopole antenna is paired with parasitically coupled SRRs. The latter elements are tuned using a capacitive load which serves to control their resonance frequency without changing their physical dimensions. These techniques have been compared with an unloaded monopole and they provide a gain enhancement of about 1 dBi within the band of interest without significantly increasing the overall antenna size which was fixed to 1.296 × 1.508 mm2.
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