Gain compensation approach for low‐voltage ride‐through and dynamic performance improvement of three‐phase type‐3 PLL

Abstract

Despite the ability of type-3 phase-locked loop (PLL) to provide zero steady-state error when a three-phase voltage experiences frequency ramp change, its major drawback is slow dynamic performance and instability during voltage sag condition. In this paper, by obtaining the linearised model of PLL, instability associated with the presence of voltage amplitude within the PLL control loop is illustrated. Furthermore, analysis of two common techniques employed in improving PLL stability (high phase margin design and use of phase-lead compensator) is presented and their inapplicability to three-phase type-3 PLL is revealed. Thus, to address the said problems, a gain compensation technique is proposed in this paper. In the proposed approach, the PLL loop gain is adjusted by inserting a DC gain within the PLL control loop when the frequency of supply voltage deviates from its nominal value. The inserted DC gain compensates for reduction in voltage amplitude within the PLL control loop, thus, enhancing PLL's stability especially during voltage sags. Also, the gain increases PLL's bandwidth thereby improving its estimation speed. Effectiveness of the proposed solution is confirmed through experimental studies and it is compared with five existing type-3 PLL schemes and a type-2 PLL.