Abstract
Two GaAs MESFET implementations of differential pass-transistor logic (DPTL) are presented. The DPTL logic technique combines the area efficiencies and high operation speeds of ratioless pass-transistor circuits with the additional features of noise immunity and low power dissipation. Circuit structures are presented for both depletion (D)-mode and enhancement/depletion (E/D)-mode MESFET technologies, and are compared with buffered FET logic (BFL) and direct-coupled FET logic (DCFL), respectively. Experimental results are provided to verify the functionality and the performance features of both DPTL forms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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