GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips

Chiara Ramella,Marco Pirola,Abbas Nasri,Motahhareh Estebsari

doi:10.3390/electronics10233029

Chiara Ramella, Marco Pirola + Show 2 more

Open Access

https://doi.org/10.3390/electronics10233029

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Journal: Electronics	Publication Date: Dec 4, 2021
Citations: 1	License type: CC BY 4.0

Affiliation: Polytechnic University of Turin

Abstract

Microwave core-chips are highly integrated MMICs that are in charge of all the beam-shaping functions of a transmit-receive module within a phased array system. Such chips include switches, amplifiers and attenuators, phase shifters, and possibly other elements, each to be controlled by external digital signals. Given the large number of control lines to be integrated in a core-chip, the embedding of a serial to parallel interface is indispensable. Digital design in compound semiconductor technology is still rather challenging due to the absence of complementary devices and the availability of a limited number of metallization layers. Moreover, in large arrays, high chip yield and repeatability are required. This paper discusses and compares challenges and solutions for the key sub-circuits of GaAs serial to parallel converters for core-chip applications, reviewing the pros and cons of the different implementations proposed in the literature.

Highlights

Active electronically scanned Array (AESA) antennas allow for controlling the beam shape and direction without physically moving the antenna since phase and amplitude of the signals driving each radiating element are independently set through a dedicated transmit-receive module (TRM), digitally controlled by a central processor
It is composed of an n-bit shift register (SR) coupled with an n-bit hold register (HR), typically completed by n output buffers (OB), input level shifters (LS) for voltage level compatibility among different logic families and Schmitt trigger input buffers
Gallium arsenide transistors are characterized by a Schottky barrier, which leads to forward gate conduction and voltage clamping and to a reduced voltage swing compared to silicon-based MOS technology

Summary

Introduction

Active electronically scanned Array (AESA) antennas allow for controlling the beam shape and direction without physically moving the antenna since phase and amplitude of the signals driving each radiating element are independently set through a dedicated transmit-receive module (TRM), digitally controlled by a central processor. The large number of transistors required in logic circuits, make the SIPO interface one of the most critical blocks in a CC in terms of yield [7]. High-frequency Si-based processes, RF-CMOS and SiGe BiCMOS, provide easier implementation of digital circuits, thanks to the availability of complementary devices and a large number of metallization layers, and have advantages in terms of noise margins, cost and yield over GaAs-based technologies [9,10,11,12]. For the same device periphery, GaAs transistors can achieve higher commutation speed than Si ones and at a lower power [9,13,14] This makes GaAs an appealing alternative to Si for high-speed logic circuits, especially when considering Enhancement/Depletion-mode (E/D-mode) technologies offering much more flexibility than D-mode-only processes for digital design.

Literature Overview of SIPO Interfaces in GaAs Microwave Core-Chips

Circuit Architecture

GaAs-Based Logic Gates

Memory Blocks

Findings

Conclusions