Abstract
A thermal fatigue life prediction model of microelectronic chips based on thermal fatigue tests and solder/substrate interfacial singularity analysis from finite element method (FEM) analysis is established in this paper. To save the calculation of interfacial singular parameters of new chips for life prediction, and improve the accuracy of prediction results in actual applications, a hybrid genetic algorithm–artificial neural network (GA–ANN) strategy is utilized. The proposed algorithm combines the local searching ability of the gradient-based back propagation (BP) strategy with the global searching ability of a genetic algorithm. A series of combinations of the dimensions and thermal mechanical properties of the solder and the corresponding singularity parameters at the failure interface are used to train the proposed GA-BP network. The results of the network, together with the established life prediction model, are used to predict the thermal fatigue lives of new chips. The comparison between the network results and thermal fatigue lives recorded in experiments shows that the GA-BP strategy is a successful prediction technique.
Highlights
Microelectronic chips are becoming more popular, because their design in smaller dimensions meets the requirements of semiconductor packaging in terms of high-density and cost-effective performance
It is of practical importance to model these stresses using analytical tools, so that the susceptibility to thermal mechanical failure can be predicted for chips with new geometries and material combinations, without costly trial and error
Method of the back propagation (BP) Artificial Neural Network Based on a Genetic Algorithm
Summary
Microelectronic chips are becoming more popular, because their design in smaller dimensions meets the requirements of semiconductor packaging in terms of high-density and cost-effective performance. The solder layer plays an important role in the mechanical and electric connections of the chip; its performance, especially the thermomechanical properties of the solder, has become an important factor affecting the reliability of microelectronic chips [1,2,3]. Due to the difference in the coefficients of thermal expansion (CTE) of various components, stress and strain always occur and gradually accumulate at the solder joints during temperature cycling. It is of practical importance to model these stresses using analytical tools, so that the susceptibility to thermal mechanical failure can be predicted for chips with new geometries and material combinations, without costly trial and error
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