GA-based design of multiplierless 2-D state-space digital filters with low roundoff noise

Abstract

A new design method for multiplierless two-dimensional (2-D) state-space digital filters (SSDFs) with very low roundoff noise is presented. To eliminate multipliers in the hardware implementation, multiplierless 2-D SSDFs are designed under the constraint that all coefficients are expressed as one or two powers-of-two terms. They are attractive for low-cost implementation and high-speed operation. In addition, they can also perform highly accurate 2 D digital filtering because of very low roundoff noise. A combinatorial optimisation method based on a genetic algorithm (GA) is given to determine the coefficients. A stability test routine is also embedded in the GA-based design procedure to ensure the stability of the resultant multiplierless SSDFs. The proposed method can design multiplierless 2-D SSDFs not only with small approximation error but also with almost minimum roundoff noise. In addition they require fewer computational volume than 2-D SSDFs designed in a continuous coefficient space. For 16-bit words, the designed multiplierless 2-D SSDFs can be implemented with 24%, of the computational volume of 2-D SSDFs with real multipliers. The effectiveness of the proposed methods is demonstrated by two design examples.