Abstract
A true technological explosion has taken place in the computer hardware industry in the last few years. Words such as parallel processing, vector processors, array processors, pipelined machines, ‘number crunching’, and megaflops ( Millions of FLoating-point OPerations per Second) are heard regularly. Computer manufacturers have responded to the needs of specific groups requiring, above all else, high speed arithmetic capability. The result is a host of new machines which are called in this paper ‘vector processors’. This paper will assess the applicability of vector processors to power flow and transient stability simulation programs and will indicate how these programs should be organized to run efficiently on these new machines. The approach taken will be to survey the entire class of vector processors available now and in the near future, to attempt to raise the reported low efficiency of sparsity-coded programs for large vector processors by reorganizing their sparse structure.
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