Abstract
Processing-in-memory (PIM) architectures show the advantage of handling applications that generate complicated memory request patterns; usually, those kinds of memory streams degrade the application’s performance in conventional memory hierarchy systems. In particular, deep convolutional neural networks (DCNNs) processing that consists of several functionalities could be highly optimized if PIM cores can extend the processing capability and data accessibility. In this work, we propose a functionality-based PIM accelerator for DCNNs. We design several modules in addition to the conventional PIM system based on a hybrid memory cube (HMC). First, we compose a new buffer module, namely, a shared cache, in which PIM cores are provided DCNN functionalities and pre-trained weights. The PIM cores subsequently enhance computational utilization and data accessibility. Second, an efficient replacement method complements the shared cache to optimize the data miss rate of DCNN processing. Third, we compose dual prefetchers that can deal with DCNN’s memory access patterns, thereby reducing the system’s overall latency. Fourth, we compose a PIM scheduler for PIM core-level autonomous request control. The PIM scheduler relieves the host processor of significant computational loads, achieving the overall latency of the system and reducing the energy consumption. By the performance evaluation based on the trace-driven HMC simulator, our proposed model improves average latency and bandwidth by 38.9 and 27.9 % with only 18.7 % more energy consumption compared with conventional HMC-based PIM systems. Our system also achieves scalable processing performance because when the DCNN becomes deeper, it processes faster than conventional PIM systems.
Highlights
In the era of the fourth industrial revolution, various cutting-edge technologies, such as artificial intelligence, robotics, 5G network, and internet-of-things, have been integrated for intelligent service automation
deep convolutional neural networks (DCNNs) functionality-based requests could be processed by the PIM core which is configured with simple in-order core in our assumed PIM system. â—Ź We composed simple dual prefetchers in each PIM core to deal with patterned memory access of DCNN workloads. â—Ź We introduced a PIM scheduler with several functions for PIM core-level autonomous request control
The shared cache has high energy requirements because the DCNN’s functional primitives are provisioned to multiple PIM cores, the PIM system’s energy was significantly reduced when the PIM scheduler was added, and the values were lower than the baseline in LeNet, which represents the effect of a significant energy reduction in the SerDes link as the PIM scheduler allowed for PIM core-level autonomous request control without the aid of the host processor
Summary
In the era of the fourth industrial revolution, various cutting-edge technologies, such as artificial intelligence, robotics, 5G network, and internet-of-things, have been integrated for intelligent service automation. In the recent literature, small-sized convolution filters, such as 1 × 1 or 3 × 3 size, were used to reduce the dimensions of feature maps [2], and residual blocks were used to make shortcuts in a feed-forward network [3], resulting in low data locality and frequent memory accesses These computational overheads have increased the demand for effective accelerating architectures. Different from the conventional PIM architectures (e.g., HMC (Section II-A)) which used PIM cores only as distributed near memory calculators to operate atomic instructions offloaded from the host processors, the PIM scheduler comprises several function calls that allow multiple PIM cores to control DCNN’s requests autonomously.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
