Abstract
The process of functional verification used in electronic design automation implies checking that the logic design conforms to its specifications. A verification environment is built to provide scenarios to be checked. The simulation environment contains the following blocks: generator (generates inputs), driver translates the input stimuli provided by the generator into input for the design under verification (DUT), score-boards database (simulates the correct behavior of the DUT and is used as reference for the verification), and different metrics of coverage. Another target of the functional verification besides checking the equivalence between DUT behavior and its specification is to obtain 100% coverage. The coverage plan is represented by the sum of all scenarios on which the DUT will be exposed.
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