Functional units power gating in SMT processors

Abstract

Power consumption has emerged as a primary concern in processor design constraints. Power-aware techniques are being applied at all levels of circuit and system design. These techniques aim at reducing power or energy dissipation in all types of computer equipments while meeting a desired throughput. At the architectural level, power-aware design has been an active area of research in the last decade for superscalar processors. Simultaneous multithreading processor (SMT), introduced as a complementary architecture to superscalar to increase throughput, has received less attention in the context of low-power design techniques. In SMT processors functional units are one of the major power consumers. In this paper we first study the opportunity for reducing the power consumption of functional units. Our results show that functional units are idle for a significant portion of the total execution cycle. Then we reuse and evaluate a microarchitectural technique to reduce functional unit power through power gating which has been recently proposed for superscalar processors. We show that in SMT processors, this technique can reduce floating point unit power considerably while maintaining performance.