Functional test generation for pipelined computer implementations

Abstract

An implementation-dependent functional testing methodology is developed for pipelined CPU implementations. The magnitude of pipeline design errors is established through the study of the design log of a commercial computer system. A model for determining the correctness of the execution of a machine language program is developed. The basis for functional pipeline test generation, the dependency graph, is introduced. A quantitative analysis of the number of dependency arcs exercised by a given instruction stream is developed. Techniques to reduce the complexity are also introduced. A methodology for generating pipeline functional test modules for a pipelined implementation is developed. Application of the methodology to a military standard computer architecture, the MIL-STD-1750A, is described. The results for the test generator, called AUTOGEN, show two orders of magnitude reduction of the test length over the standard comprehensive architectural verification program. >