Functional test generation for FSMs by fault extraction

Abstract

Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG algorithms utilize a functional description of a circuit. Multi-level TPG algorithms attempt to realize the advantages of both approaches through fault translation. In such systems, gate-level faults are translated to functional faults and TPG is performed at the functional level. We develop and present new techniques for fast efficientfault translation from the logic to the functional level. These techniques are implemented in a multi-level sequential circuit test generation system. Performance results for benchmark circuits are presented.