Functional test circuits employing ion-implanted propagation patterns

Abstract

Functional eight and six micron period bubble test devices based on ion-implanted propagation are discussed. Generation, transfer, expansion and annihilation were implemented in a 5000Å thick Al-Cu layer. The magnetoresistive detector itself was defined in a 500Å layer of Permalloy. The features were all 2 μm or larger at 8 μm period. The 6 μm period circuits were obtained by making all features 25% smaller, using an EBES option. The standard implantation conditions used for these devices were 80/Ne/1E14 (unpatterned) + 270/ Ne/2E14 + 130/H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> /2E16. Modified implantation conditions, which replaced the large H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> + dose by a smaller He+ implant, were analyzed by FMR and x-ray diffraction. Eight micron period propagation data, obtained with this change in implantation, is presented for 200 kHz triangular drive. A novel approach to microcomputer test set control was used to measure separate bias margins for 1)serial operation from generator through the write line to the read line and on to the detector (G-loop), 2)write line transfer, 3)read line transfer, and 4) minor loop propagation. Single bubble bias margins vs drive field for these tests were obtained at 8 and 6 μm period. Improved current margins, obtained with new stretcher and read-line transfer designs, are shown at 8 μm period. The 8 μm period test circuit was also expanded into a nominally 256 k-bit device. Actually, 256 loops of 1033 bits each were obtained on a chip 5 × 6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Bias margins are displayed vs drive field for the G-loop and vs the degree of redundancy postulated for the minor loops. Over 90% of the loops had full margins at 40 Oe drive. The implant level of the particular 256 k device discussed was exposed using a 1:1 projection aligner. Finally a full 2-in. wafer was devoted to a single circuit, also at 8 μm period. There were 1,792 loops of 6441 bits each grossing over 11.5 M-bits on the 30 × 28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip. Bias margins were plotted vs drive field for the serial paths on a particular chip which had 1350 good loops (or over 1 M-byte).