Functional coverage measurements and results in post-Silicon validation of Core™2 duo family

Abstract

Post-Silicon verification is an activity that is still maturing with respect to functional coverage methodologies. The architectural and micro-architectural feedback from silicon can be used to enhance the level of quality of the test suite, and allows monitoring the frequency of interesting micro-architectural events. For the latest Intel Corporation’s multi-core processors (Intel® Core™2 Duo processor, Intel® Core™2 Extreme processor, Dual-Core Intel® Xeon® processor 5100 series, Intel® Core™2 Duo mobile processor,), validation uses Random Instruction Tool (RIT) generated tests, so the need for coverage increases in importance. There are different methods that are used to understand what the RIT is exercising. In this paper, three efficient orthogonal solution and results vectors are presented: (A) Front-Side-Bus (FSB) Checker and coverage approach exploiting the re-use of mature pre-silicon tools, (B) Extended Execution Trace (EET) mechanism which uses special microcode patches for external tracking of microcode flows, and (C) Performance Monitoring Hardware used to collect frequency coverage of specific internal events. With these approaches, effective Front-Side Bus, microcode and architectural coverage was collected, analyzed and used as feedback for better tuning the RIT generation parameters. These three solutions have been put to practice in projects code named Conroe, Woodcrest, Merom, and Penryn to further improve the quality of test generated by the System Validation’s (SV) RIT.