Functional and Linearity Test System for the LHC Beam Loss Monitoring Data Acquisition Card

Abstract

In the frame of the design and development of the Beam Loss Monitoring (BLM) system for the Large Hadron Collider (LHC) a flexible test system has been developed to qualify and verify during design and production the BLM LHC data acquisition card. It permits to test completely the functionalities of the board as well as realizing analog input signal generation to the acquisition card. The system utilize two optical receivers, a Field Programmable Gate Array (FPGA), eights flexible current sources and a Universal Serial Bus (USB) to link it to a PC where a software written in LabWindows/CVI© (National Instruments) runs. It includes an important part of the measurement processing developed for the BLM in the future LHC accelerator. It is called Beam Loss Electronic Current to Frequency Tester (BLECFT).