Abstract
A set of VLSI architectures for robot direct kinematics computation is presented. The homogeneous link transformation matrix is decomposed into products of translation/rotation matrices, each of which is implemented via an augmented CORDIC as a processing element. A specific scheme is proposed for a six-link robot kinematics processor utilizing full pipelining at the macro level and parallel redundant arithmetic and full pipelining at the micro level. The performance of the scheme is analyzed with respect to the time to compute one location of the end-effector of a six-link manipulator and the number of transistors required. This scheme is assessed to produce a single-chip VLSI utilizing state-of-the-art MOS technology. A comparison table shows that the CORDIC-based robotics processor is a prospective solution in VLSI to be used for a wide range of kinematic calculation requirements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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