Abstract
In this paper, fully-synthesizable Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) suitable for low-cost integrated systems are proposed both for voltage and current input. The proposed ADCs are digital in nature and are based on the Dyadic Digital Pulse Modulation (DDPM) Digital-to-Analog (DAC), instead of a traditional capacitive DAC. The proposed fully-digital ADC architectures enable low-effort design, silicon area reduction, and voltage scaling down to the near-threshold region. Compared to traditional analog-intensive designs, their digital nature allows easy technology and design porting, digital-like area shrinking across CMOS technology generations, and also drastically reduced system integration effort through immersed-in-logic ADC design. The voltage-input ADC architecture is demonstrated with a 40-nm testchip showing 3,000-μm 2 area, 6.4-bit ENOB, 2.8kS/s sampling rate, 40.4dB SNDR, 49.7dB SFDR, and 3.1μW power at 1V. A current-input ADC is also demonstrated for direct current readout without requiring a trans-resistance stage. 40-nm testchip measurements show a 5-nA to 1-μA input range, 4,970μm 2 area, 6.7-bit ENOB and 2.2-kS/s sample rate, at 0.94-μW power. Compared to the state of the art, the proposed ADC architecture exhibits the highest level of design automation (standard cell), lowest area, and the unique ability to cover direct acquisition of both voltage and current inputs, suppressing the need for transresistance amplifier in current readout.
Highlights
Analog-to-digital converters are essential building blocks in systems-on-chip embedding sensing capabilities
FULLY-SYNTHESIZABLE VOLTAGE-INPUT Analog-to-Digital Converters (ADCs): EXPERIMENTAL RESULTS The proposed ADC-V was implemented in the 40nm CMOS testchip shown in Fig. 3, and occupies a silicon area of 3,000μm2
In this paper, standard cell-based Nyquist-rate Dyadic Digital Pulse Modulation (DDPM) ADCs have been explored in terms of architectures, as well as in terms of their limits and potential for moderate resolutions
Summary
Analog-to-digital converters are essential building blocks in systems-on-chip embedding sensing capabilities. Sigma-Delta ( ) MASH ADCs (e.g., [13]) achieve the highest resolution at relatively low sample rates, but require significant analog design in addition to their digital components. A Nyquist-rate fully-synthesizable SAR voltage-input ADC based on the Dyadic Digital Pulse Modulation (DDPM) is proposed. The proposed ADCs exhibit the lowest area and the highest resolution among mostly- and fully-digital ADCs to date, while being designed with fully-automated digital design flows This allows the highest level of design automation and integration with digital logic, substantially reducing design and system integration effort via immersed-in-logic implementation, compared to traditional analog architectures. This comprises only logic gates and two passive components, which can all be instantiated, placed and routed automatically (i.e., through scripting, without requiring any analog design). Architecture of the proposed standard cell-based voltage-input Analog-to-Digital Converter (ADC-V). Which is proportional to the analog input vIN /VDD normalized to the dynamic range, as expected from an ADC
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