Fully Printed Zinc Oxide Electrolyte-Gated Transistors on Paper.

José Carvalho,Viorel Dubceac,Paul Grey,Inês Cunha,Luís Pereira,Elvira Fortunato,Andre Clausner,Ehrenfried Zschech,Rodrigo Martins

doi:10.3390/nano9020169

Abstract

Fully printed and flexible inorganic electrolyte gated transistors (EGTs) on paper with a channel layer based on an interconnected zinc oxide (ZnO) nanoparticle matrix are reported in this work. The required rheological properties and good layer formation after printing are obtained using an eco-friendly binder such as ethyl cellulose (EC) to disperse the ZnO nanoparticles. Fully printed devices on glass substrates using a composite solid polymer electrolyte as gate dielectric exhibit saturation mobility above 5 cm2 V−1 s−1 after annealing at 350 °C. Proper optimization of the nanoparticle content in the ink allows for the formation of a ZnO channel layer at a maximum annealing temperature of 150 °C, compatible with paper substrates. These devices show low operation voltages, with a subthreshold slope of 0.21 V dec−1, a turn on voltage of 1.90 V, a saturation mobility of 0.07 cm2 V−1 s−1 and an Ion/Ioff ratio of more than three orders of magnitude.

Highlights

Printed electronics (PE) has attracted strong interest among researchers aiming to introduce simpler fabrication techniques for low cost consumer electronics
Due to their low operation voltages (
This study reports the development of fully printed EGTs, based on an interconnected zinc oxide (ZnO) nanoparticle matrix, arranged in a staggered-top gate architecture

Summary

Introduction

Printed electronics (PE) has attracted strong interest among researchers aiming to introduce simpler fabrication techniques for low cost consumer electronics. Applying a voltage to the gate electrode causes ion migration in the electrolyte, leading to the formation of an electric double layer (EDL) at the electrolyte/channel interface This results in large gate capacitance (virtually independent of the thickness) in the order of 1–10 μF cm−2, enabling charge accumulation into the semiconductor at low gate voltages [3]. This makes EGTs very attractive for PE, where thin insulating dielectric layers capable of providing high gate capacitance are difficult to obtain by printing techniques at temperatures compatible with paper substrates [4,5,6,7]. Due to their low operation voltages (

Methods

Results

Conclusion