Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling

Abstract

An incoherent subsampling scheme for on-chip measurement of high-speed clock jitter and skew is presented. A simple inverter-based ring oscillator with frequency selection multiplexers is used to generate uniform and uncorrelated sampling events when binned in the unit period of the clock. The measurement results are directly reflected in the on-chip counters which are proportional to the injected jitter and skew. The measurement errors can be reduced with increasing sampling numbers. Theories of ring oscillator period suitability, sampling number requirement and jitter measurement are analyzed in detail. Behavioral simulations using MATLAB are performed to verify the proposed theories. The measurement circuit is implemented using a 55 ​nm CMOS process and the maximum measurement errors in skew mode and jitter mode from SPICE simulations are 0.121ps and 0.123 ​ps, respectively. The implemented measurement circuit has good immunity to PVT variations after proper tuning and the influence of supply noise is also investigated.