Abstract
Implementation of a buried p-layer in a fully ion implanted InP JFET is discussed. Using Be coimplanted with Si, a sharp channel profile is obtained. The saturation current has been reduced, and the pinch-off characteristic has been improved, with a slight decrease in transconductance and cutoff frequency. The equivalent circuits for the JFET with and without the buried p-layer are compared.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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