Abstract
Threshold voltage (Vth) controllability of diffusion self-aligned (DSA) MOS FET fabricated by a full ion implantation and N2 drive-in technique has been examined and analyzed. As the p-type diffused region (base) and the n-type diffused region (source) were formed by this method, the impurity profiles of these layers became reproducible and Vth controllability were improved as compared with the usual thermal predeposition process. A simplified Vth model showed a good agreement with the experimental results. The performance of DSA ED MOS IC has been also discussed. In the 19 stage ring oscillators, the propagation delay time per unit gate was 0.36 ns (Vdd=8.0 V) for high speed design and the power-delay product was 0.055 pJ (Vdd=2.7 V) for low power design. A 1024-bits random access memory has been developed on the basis of above mentioned results, and the access time of 50 ns has been obtained.
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