Abstract
This letter discusses the integration of Class-J power amplifiers (PA). A set of modified design equations considering harmonic losses is derived and the inductor losses are discussed. Based on the discussion, a fully integrated Class-J PA with stacked-FET structure is designed and implemented in a $0.18~\mu \text {m}$ CMOS process. The proposed Class-J PA, powered by a 3.3 V supply, achieves a power-added efficiency (PAE) and drain efficiency (DE) of 43.7% and 45.1%, respectively, with a saturated output power of 22 dBm. Along with a maximum gain of 17.4 dB, the broadband PA exhibits a 3-dB band from 2.1 GHz to 4.8 GHz.
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