Fully digital synchronous frequency doubler for FM stereo decoder

Abstract

In this paper, we present a fully digital synchronous architecture for doubling the frequency of a pilot tone in FM stereo decoder. The proposed architecture uses two phase shifters ±45° and an X-OR gate. A phase difference of 90° differential is obtained between the outputs of the phase shifters. The two phase shifter outputs are edge combined by an X-OR operation to generate an output signal that has twice the frequency of the input signal with 50% duty cycle. The phase shifters are implemented by a pair of linear FIR filters having identical magnitude and orthogonal phase responses. Hardware optimization of FIR filters are done to reduce the area overhead due to two filters. The frequency doubling of pilot tone (19 KHz used in FM Stereo decoder) with 50% duty cycle is experimentally verified using Spartan-6 FPGA. The proposed frequency doubler can be used only on receiver side of communication system.