Full-chip poly gate critical dimension control using model based lithography verification

Abstract

Gate CD (Critical Dimension) control is an important factor in determining semiconductor manufacturing yield. Therefore, its verification prior to mask tape-out is essential to save development time and cost. Not only is fatal-error detection required to ensure high yield, tight CD control in the gate region is equally critical in sub-micron IC manufacturing. As fast turn around time is achieved for very large data through scalable distributed processing, model-based lithography verification has been utilized for checking the post mask synthesis data quality before mask tape out and RET/OPC process development. In this paper, we introduce a comprehensive methodology to study and qualify Poly mask layer using a model based lithography verification tool. This flow will include CD checks on both gate-width and gate- length dimensions. Gate CD distribution plots on the poly layer will be done across a complete range of target CDs in order to investigate wafer CD uniformity errors on full-chip level under various process conditions. In addition, the traditional edge-placement detection will be discussed and compared to absolute CD verification process.