Full operation of a three-node pipeline-ring switching chip for a superconducting network system

Abstract

We report on the full circuit operation of a switching core chip for a superconducting network system. Our network fabric is a pipeline-ring architecture. Our ring network has a unidirectional data flow. This configuration provides increases of switching performance in two ways: a larger throughput means that many cells can occupy the ring bus at the same time, and a shorter operation time means that the bus occupation control only needs to check whether the data exists on the connected local part of the bus. The circuit consists of three ring interface circuits (RIFs), a slot repeater (SR) circuit, and superconducting interconnections. Each RIF has an address. The main functions of the switching circuit are the following: (a) decoding of packet addresses and routing, (b) arranging the blocking of data between incoming data from the processor and network, and (c) redefining (changing the validity) of slots. We designed the circuit with a voltage-level bipolar-powered logic family. There are about 4300 Josephson junctions in the whole circuit and it measures about 3.3 mm/spl times/2.5 mm. We successfully tested these functions and demonstrated data exchange in the whole circuit. We were also able to confirm correct operation up to 2-GHz clock frequency by using an on-chip self-testing method.